Machine Learning and Deep Learning in Wafer Defect Detection: Current State and Future Directions
Balachandar Jeganathan
*
ASML, San Jose, CA, USA.
*Author to whom correspondence should be addressed.
Abstract
The semiconductor manufacturing industry demands increasingly sophisticated quality control mechanisms as device miniaturization approaches atomic scales. Wafer defect detection, a critical component of semiconductor fabrication, has undergone significant transformation with the advent of machine learning (ML) and deep learning (DL) technologies. This comprehensive review examines the current state of ML/DL applications in wafer defect detection, analyzing the evolution from traditional rule-based systems to advanced neural architectures including convolutional neural networks (CNNs), vision transformers, and multimodal fusion approaches. Unlike previous reviews, this work provides the first unified comparison of CNN-, Transformer-, and hybrid multimodal architectures on major wafer-map benchmarks, while also synthesizing production-oriented considerations such as real-time deployment constraints and integration challenges. Performance across major datasets is systematically evaluated, critical challenges in sub-5nm detection scenarios are identified, and future research directions are outlined. While current DL methods achieve accuracies exceeding 98% (Xu et al., 2023), significant challenges remain in real-time processing, mixed-type defect classification, and integration with existing manufacturing systems. Comprehensive data sources, implementation frameworks, and key research opportunities are provided, including explainable AI, few-shot learning, and edge computing solutions for next-generation semiconductor manufacturing.
Keywords: Wafer defect detection, deep learning, computer vision, semiconductor manufacturing, quality control, machine learning wafer defect detection, DEEP learning, machine learning